CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

22.3 Derating

The AC timings included with each timing diagram include only the intrinsic delay through the output pads.

In order to calculate actual delays when designing the CL-PS7500FE into a system, it is necessary to add

the load-dependent element of the output pad delay.

The output pads of CL-PS7500FE are CMOS drivers which exhibit a propagation delay that increases lin-

early with the increasing capacitance. An Output derating figure is provided for each of the three types of

output pads, showing the increase in output delay with increasing load capacitance.

Details about which driver is used for which output can be found in Chapter 2.

Derating figures are quoted for rising and falling edges.

Table 22-1. CL-PS7500FE Pad Derating

Label

x1

x2

x3

Pad Type

Low drive capability pad

Medium drive capability pad

High drive capability pad

Rising

0.18

0.061

0.029

Falling

0.16

0.046

0.019

Units

ns/pF

ns/pF

ns/pF

198

ELECTRICAL SPECIFICATIONS

ADVANCE DATA BOOK v2.0

June 1997

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