CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

D[31:16]

16

16

ARM7500

nWBE

nRBE

nBLO

EN

DQ

G

BDHI[15:0]

16

EN

QD

16

G

I/O Device

LA[9:0]

10

BD[15:0]

16

nIOW

nIOR

eg. nCCS

CLK16

Figure D-1. 32-bit I/O Interface

The write and read path each contain a 16-bit latch with tristate output enable control:

q The write latch latches data from D[31:16] when nBLO is high and drive the latched data onto the expanded

I/O bus, BDHI[15:0], when nWBE is active-low.

q The read latch should latch data from BDHI[15:0] when nBLO is high and drive the latched data onto

D[31:16], when nRBE is active-low.

NOTE: Like the BD[15:0] bus, the write enable nWBE remains active-low by default. It is deasserted only during the

read cycles, thus the I/O device must not attempt to drive BD[15:0] or BDHI[15:0], except when a read cycle

occurs.

June 1997

ADVANCE DATA BOOK v2.0

235

Share Link: