CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

HCLK

VCLK

VCLKO

PCOMP

CON_REG[1:0]

CON_REG[4:2]

PHASE

COMPARATOR

DIVIDE BY N

PIXCK

INTERNAL IOCK32

Figure E-1. Video and Sound Macrocell Internal Clock System

3. Using the Phase Comparator

The video and sound macrocell contains a phase comparator that, in conjunction with an external VCO,

can build a PLL.

The phase comparator contains:

q two counters

q a phase detector

The counters are pre-loadable down counters, one clocked from the internal IOCK32 signal derived from

I_OCLK, and the other clocked from VCLKI. The moduli of the counters is programmed in the Frequency

Synthesizer register.

In the Frequency Synthesizer register, the test bits are:

bit 6

force PCOMP high and driven

bit 7

clear r-modulus counter

bit 14

force PCOMP low and driven

bit 15

clear v-modulus counter

June 1997

ADVANCE DATA BOOK v2.0

237

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