CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

6.11.1 Interaction of the MMU, IDC, and Write Buffer

The MMU, IDC, and WB can be enabled/disabled independently. However there are only five valid com-

binations. There are no hardware interlocks on these restrictions, so invalid combinations cause unde-

fined results.

Table 6-6. Valid MMU, IDC, and WB Combinations

MMU

IDC

WB

Off

Off

Off

On

Off

Off

On

On

Off

On

Off

On

On

On

On

The following procedures must be observed.

Enable the MMU

1. Program the TTB and Domain Access Control registers.

2. Program Level One and Level Two page tables as required.

3. Enable the MMU by setting bit 0 in the Control register.

NOTE: Care must be taken if the translated address differs from the untranslated address as the two instructions

following the enabling of the MMU are fetched using ‘flat translation’ and enabling the MMU may be consid-

ered as a branch with delayed execution. A similar situation occurs when the MMU is disabled. Consider the

following example code sequence:

MOV

R1, #0x1

MCR

15,0,R1,0,0

; Enable MMU

Fetch Flat

Fetch Flat

Fetch Translated

Disable the MMU

1. Disable the WB by clearing bit 3 in the Control register.

2. Disable the IDC by clearing bit 2 in the Control register.

3. Disable the MMU by clearing bit 0 in the Control register.

NOTE: If the MMU is enabled, then disabled, then subsequently re-enabled the contents of the TLB are preserved.

If these are now invalid, the TLB should be flushed before re-enabling the MMU.

Disabling of all three functions can be done simultaneously.

June 1997

ADVANCE DATA BOOK v2.0

51

ARM PROCESSOR MMU

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