CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

remove the need for register saving in such applications (thus minimizing the overhead of context switch-

ing).

NOTE: The FIQ exception can be disabled by setting the F flag in the CPSR (but note that this is not possible from

User mode).

If the F flag is clear, the ARM processor checks for a low level on the output of the FIQ synchronizer at

the end of each instruction. When a FIQ is detected, the ARM processor performs the following:

1) Saves the address of the next instruction to be executed plus 4 in R14_fiq; saves CPSR in SPSR_fiq.

2) Forces M[4:0]=10001 (FIQ mode) and sets the F and I bits in the CPSR.

3) Forces the PC to fetch the next instruction from address 0x1C.

Returning from FIQ

To return normally from FIQ, use SUBS PC, R14_fiq, #4 to restore both the PC (from R14) and the CPSR

(from SPSR_fiq) and resume execution of the interrupted code.

7.4.2 IRQ

The IRQ (Interrupt ReQuest) exception is a normal interrupt caused by the interrupt handler within the

CL-PS7500FE. It has a lower priority than FIQ, and is masked out when a FIQ sequence is entered. Its

effect can be masked out at any time by setting the I bit in the CPSR (but note that this is not possible

from User mode).

If the I flag is clear, the ARM processor checks for a low level on the output of the IRQ synchronizer at the

end of each instruction. When an IRQ is detected, the ARM processor performs the following:

1) Saves the address of the next instruction to be executed plus 4 in R14_irq; saves CPSR in SPSR_irq.

2) Forces M[4:0]=10010 (IRQ mode) and sets the I bit in the CPSR.

3) Forces the PC to fetch the next instruction from address 0x18.

Returning from IRQ

To return normally from IRQ, use SUBS PC,R14_irq, #4 to restore both the PC and the CPSR and resume

execution of the interrupted code.

7.4.3 Abort

An abort is signalled by the internal MMU and indicates that the current memory access cannot be com-

pleted. For instance, in a virtual memory system the data corresponding to the current address may have

been moved out of memory onto a disk, and considerable processor activity may be required to recover

the data before the access can be performed successfully.

The abort mechanism allows a demand paged virtual memory system to be implemented when suitable

memory management software is available. The processor is allowed to generate arbitrary addresses,

and when the data at an address is unavailable, the MMU signals an abort. The processor traps into sys-

tem software that must then work out the cause of the abort, make the requested data available, and retry

the aborted instruction. The application program needs no knowledge of the amount of memory available

to it, nor is its state in any way affected by the abort.

58

REGISTER DESCRIPTIONS

ADVANCE DATA BOOK v2.0

June 1997

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