CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

The ARM processor checks for ABORT during memory access cycles. When successfully aborted the

ARM processor responds in one of two ways:

q a prefetch abort

q a data abort

Prefetch Abort

If the abort occurred during an instruction prefetch (a prefetch abort), the prefetched instruction is marked

as invalid but the abort exception does not occur immediately. If the instruction is not executed, for exam-

ple, as a result of a branch being taken while it is in the pipeline, no abort occurs. An abort takes place if

the instruction reaches the head of the pipeline and is about to be executed.

Data Abort

If the abort occurred during a data access (a data abort), the action depends on the instruction type:

q Single data transfer instructions (LDR and STR) write back modified base registers and the Abort handler

must be aware of this.

q The swap instruction (SWP) is aborted as though it had not executed, though externally the read access can

occur.

q Block data transfer instructions (LDM and STM) complete and, if write-back is set, the base updates. If the

instruction would normally have overwritten the base with data (such as, LDM with the base in the transfer

list), this overwriting is prevented. All register overwriting is prevented after the abort is indicated, which par-

ticularly means that R15 (always last to transfer) is preserved in an aborted LDM instruction.

Abort Sequence

When either a prefetch or data abort occurs, the ARM processor performs the following:

1) Saves the address of the aborted instruction plus four (for prefetch aborts) or eight (for data aborts) in

R14_abt; saves CPSR in SPSR_abt.

2) Forces M[4:0]=10111 (Abort mode) and sets the I bit in the CPSR.

3) Forces the PC to fetch the next instruction from either:

a) address 0x0C (prefetch abort), or

b) address 0x10 (data abort).

Returning from an Abort

To return after fixing the reason for the abort, use SUBS PC, R14_abt, #4 (for a prefetch abort) or SUBS

PC, R14_abt, #8 (for a data abort). This restores both the PC and the CPSR, and retry the aborted instruc-

tion.

7.4.4 Software Interrupt

The SWI gets into Supervisor mode, usually to request a particular supervisor function. When a SWI is

executed, the ARM processor performs the following:

1) Saves the address of the SWI instruction plus four in R14_svc; saves CPSR in SPSR_svc.

2) Forces M[4:0]=10011 (Supervisor mode) and sets the I bit in the CPSR.

3) Forces the PC to fetch the next instruction from address 0x08.

June 1997

ADVANCE DATA BOOK v2.0

59

REGISTER DESCRIPTIONS

Share Link: