ST72E121J4D0 查看數據表（PDF） - STMicroelectronics

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ST72E121J4D0

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS

STMicroelectronics 

ST72E121 ST72T121

POWER SAVING MODES (Cont’d)

3.4.4 Halt Mode

The Halt mode is the MCU lowest power con-

sumption mode. The Halt mode is entered by exe-

cuting the HALT instruction. The internal oscillator

is then turned off, causing all internal processing to

be stopped, including the operation of the on-chip

peripherals. The Halt mode cannot be used when

the watchdog is enabled, if the HALT instruction is

executed while the watchdog system is enabled, a

watchdog reset is generated thus resetting the en-

tire MCU.

When entering Halt mode, the I bit in the CC Reg-

ister is cleared so as to enable External Interrupts.

If an interrupt occurs, the CPU becomes active.

The MCU can exit the Halt mode upon reception of

an interrupt or a reset. Refer to the Interrupt Map-

ping Table. The oscillator is then turned on and a

stabilization time is provided before releasing CPU

operation. The stabilization time is 4096 CPU clock

cycles.

After the start up delay, the CPU continues oper-

ation by servicing the interrupt which wakes it up or

by fetching the reset vector if a reset wakes it up.

Figure 17. HALT Flow Chart

HALT INSTRUCTION

WATCHDOG Y

RESET

WDG

ENABLED?

N

OSCILL ATO R

PERIPH. CLOCK

CPU CLOCK

I-BIT

OFF

OFF

OFF

CLEARED

N

N

EXTERNAL

INTERRUPT1)

RESET

Y

Y

OSCILLATOR

ON

PERIPH. CLOCK2) OFF

CPU CLOCK

ON

I-BIT

SET

4096 CPU CLOCK

CYCLES DELAY

OSCILLATOR

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

ON

ON

SET

FETCH RESET VECTOR

OR SERVICE INTERRUPT

1) or some specific interrupts

2) if reset PERIPH. CLOCK = ON ; if interrupt

PERIPH. CLOCK = OFF

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

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