ST72E121J4D0 查看數據表（PDF） - STMicroelectronics

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ST72E121J4D0

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS

STMicroelectronics 

ST72E121 ST72T121

I/O PORTS (Cont’d)

Figure 19. I/O Block Diagram

ALTERNATE ENABLE

ALTERNATE 1

OUTPUT

M

U

X

0

VDD

P-BUFFER

(SEE TABLE BELOW)

DR

LATCH

DDR

LATCH

ALTERNATE

ENABLE

PULL-UP

CONDITIO N

PULL-UP

VDD

DIODE

(SEE TABLE BELOW)

OR

LATCH

(SEE TABLE BELOW)

ANALOG ENABLE

(ADC)

PAD

OR SEL

DDR SEL

ANALOG

S WITC H

(SEE NOTE BELOW)

GND

DR SEL

ALTERNATE INPUT

1

M

U

X

0

ALTERNATE

ENABLE

N-BUFFER

GND

EXTERNAL

INTERRUPT

SOURCE (EIx)

POLARITY

SEL

FROM

OTHER

BITS

Table 9. Port Mode Configuration

Floating

Pull-up

Push-pull

Configuratio n Mode

True Open Drain

Open Drain (logic level)

Legend:

0 - present, not activated

1 - present and activated

CMOS

SCHMITT TRIGGER

Pul l-up

0

1

0

not present

0

P-buffe r

0

0

1

not present

0

VDD Diode

1

1

1

not present

1

Notes:

– No OR Register on some ports (see register map).

– ADC Switch on ports with analog alternate functions.

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