ST72E121J4D0 查看數據表（PDF） - STMicroelectronics

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ST72E121J4D0

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS

STMicroelectronics 

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 32. SCI Block Diagram

ST72E121 ST72T121

TDO

RDI

Write

Transmit Data Register (TDR)

Read

(DATA REGIST ER) DR

Received Data Register (RDR)

Transmit Shift Register

Received Shift Register

CR1

R8 T8 - M WAKE - -

-

TRA NSMIT

CONT ROL

WAKE

UP

UNIT

CR2

TIE TCIE RIE ILIE TE RE RWU SBK

RECEIVE R

CONTRO L

RECE IVER

CLOCK

SR

TDRE TC RDRF IDLE OR NF FE -

SCI

IN TERRUPT

CONTRO L

TRANSMIT TER

CLOCK

fCPU

/16

/2

/PR

TRANS MITTER RATE

CONTRO L

BRR

SCP1SCP0SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE

CONTROL

CONVEN TIONAL BAUD RATE GENERATOR

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