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ST72E121J4D0 查看數據表(PDF) - STMicroelectronics

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ST72E121J4D0 Datasheet PDF : 92 Pages
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ST72E121 ST72T121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ERPR)
REGISTER (ETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi- Allows setting of the External Prescaler rate divi-
sion factor for the receive circuit.
sion factor for the transmit circuit.
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
7
6
5
4
3
2
1
0
7
0
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres- Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres-
caler Register.
caler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 34) is divided by
the binary factor set in the ERPR register (in the
range 1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 34) is divided by
the binary factor set in the ETPR register (in the
range 1 to 255).
The extended baud rate generator is not used af- The extended baud rate generator is not used af-
ter a reset.
ter a reset.
Table 16. SCI Register Map and Reset Values
Address
(Hex.)
50
51
52
53
54
55
57
Register
Name
SR
Reset Value
DR
Reset Value
BRR
Reset Value
CR1
Reset Value
CR2
Reset Value
ERPR
Reset Value
ETPR
Reset Value
7
6
5
4
3
2
1
0
TDRE
1
DR7
-
SCP1
0
R8
-
TIE
0
ERPR7
0
ETPR7
0
TC
1
DR6
-
SCP0
0
T8
-
TCIE
0
ERPR6
0
ETPR6
0
RDRF
0
DR5
-
SCT2
x
-
RIE
0
ERPR5
0
ETPR5
0
IDLE
0
DR4
-
SCT1
x
M
-
ILIE
0
ERPR4
0
ETPR4
0
OR
0
DR3
-
SCT0
x
WAKE
-
TE
0
ERPR3
0
ETPR3
0
NF
0
DR2
-
SCR2
x
-
RE
0
ERPR2
0
ETPR2
0
FE
0
DR1
-
SCR1
x
-
RWU
0
ERPR1
0
ETPR1
0
-
0
DR0
-
SCR0
x
-
SBK
0
ERPR0
0
ETPR0
0
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