ST72E121J4D0 查看數據表（PDF） - STMicroelectronics

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ST72E121J4D0

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS

STMicroelectronics 

ST72E121 ST72T121

SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 38. Data Clock Timing Diagram

CPOL = 1

CPHA =1

CPOL = 0

MISO

(from master)

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MOSI

(from slave)

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

SS

(to slave)

CAPTURE STROBE

CPOL = 1

CPHA =0

CPOL = 0

MISO

(from master)

MOSI

(from slave)

MSBit Bit 6

MSBit Bit 6

Bit 5 Bit 4

Bit 5 Bit 4

Bit3 Bit 2

Bit3 Bit 2

Bit 1 LSBit

Bit 1 LSBit

SS

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

VR02131B

67/92

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