ST72E121J4D0 查看數據表（PDF） - STMicroelectronics
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ST72E121J4D0
STMicroelectronics
ST72E121J4D0 Datasheet PDF : 92 Pages
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ST72E121 ST72T121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
TR dividi ng factor SCT2 SCT1 SCT0
7
0
1
0
0
0
2
0
0
1
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
4
0
1
0
8
0
1
1
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 32).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 32).
BAUD RATE REGISTER (BRR)
Read/Write
Reset Value: 00xx xxxx (XXh)
7
0
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
RR dividi ng factor SCR2 SCR1 SCR0
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
1
0
0
0
2
0
0
1
Bit 7:6= SCP[1:0] First SCI Prescaler
4
0
1
0
These 2 prescaling bits allow several standard
clock division ranges:
8
0
1
1
16
1
0
0
PR Prescaling factor
SCP1
SCP0
32
1
0
1
1
0
0
64
1
1
0
3
0
1
128
1
1
1
4
1
0
13
1
1
Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.
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