ST72E121J4D0 查看數據表（PDF） - STMicroelectronics

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ST72E121J4D0

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS

STMicroelectronics 

ST72E121 ST72T121

6.4 RESET CHARACTERISTICS

(TA=-40...+125oC and VDD=5V±10% unless otherwise specified.

Symbol

Parameter

Condition s

RON

tRESET

tPULSE

Reset Weak Pull-up RON

Pulse duration generated by watch-

dog and POR reset

Minimum pulse duration to be ap-

plied on external RESET pin

VIN > VIH

VIN < VIL

Note:

1) These values given only as design guidelines and are not tested.

Min Typ 1) Max

20

40

80

60

120 240

1

10 1)

Unit

kΩ

µs

ns

6.5 OSCILLATOR CHARACTERISTICS

(TA = -40°C to +125°C unless otherwise specified)

Symbol

Parameter

Test Conditions

gm

fOSC

tstart

Oscillator transconductance

Crystal frequency

Osc. start up time

VDD = 5V±10%

Min.

2

1

Value

Typ.

Max.

9

16

50

Unit

mA/V

MHz

ms

6.6 PERIPHERAL CHARACTERISTICS

Low Voltage Detection Reset Electrical Specifications (Optio n)

Symbol

VLVDUP

VLVDDOWN

VLVDHYS

Parameter

LVD Reset Trigger, VDD rising edge

LVD Reset Trigger, VDD falling edge

LVD Reset Trigger, hysteresis2)

Cond itions

fOSC = 8 MHz max1).

Min.

3.6 2

3.35

Typ.

3.85

3.6

250

Notes:

1. The safe reset cannot be guaranted by the LVD when fosc is greater than 8MHz.

2. Based on characterisation results, not tested.

Max.

4.1

3.85

Unit

V

V

mV

84/92

84

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