OR2T15B7BA352-DB 查看數據表（PDF） - Lattice Semiconductor

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OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

November 2006

ORCA Series 2 FPGAs

Estimating Power Dissipation (continued)

power dissipated by inputs and ac power dissipated by

outputs. The power dissipated in each I/O depends on

OR2T15B and OR2T40B

whether it is configured as an input, output, or input/

output. If an I/O is operating as an output, then there is

The total operating power dissipated is estimated by

a power dissipation component for PIN, as well as

summing the standby (IDDSB), internal, and external

power dissipated. The internal and external power is

the power consumed in the PLCs and PICs, respec-

tively. In general, the standby power is small and may

S be neglected. The total operating power is as follows:

PT = Σ PPLC + Σ PPIC

E The internal operating power is made up of two parts:

clock generation and PFU output power. The PFU out-

put power can be estimated based upon the number of

IC PFU outputs switching when driving an average fan-out

of two:

D PPFU = 0.08 mW/MHz

V E For each PFU output that switches, 0.08 mW/MHz

needs to be multiplied times the frequency (in MHz)

that the output switches. Generally, this can be esti-

E mated by using one-half the clock rate, multiplied by

U some activity factor; for example, 20%.

D The power dissipated by the clock generation circuitry

IN is based upon four parts: the fixed clock power, the

power/clock branch row or column, the clock power dis-

sipated in each PFU that uses this particular clock, and

T the power from the subset of those PFUs that is config-

T ured in either of the two synchronous modes (SSPM or

SDPM). Therefore, the clock power can be calculated

C for the four parts using the following equations:

N OR2T15B Clock Power

E P = [0.30 mW/MHz

O + (0.85 mW/MHz – Branch) (# Branches)

L+ (0.008 mW/MHz – PFU) (# PFUs)

+ (0.002 mW/MHz – SMEM_PFU)

E C (# SMEM_PFUs)] fCLK

For a quick estimate, the worst-case (typical circuit)

S IS OR2T15B clock power ≈ 3.9 mW/MHz.

OR2T40B Clock Power

D P = [0.42 mW/MHz

POUT. This is because the output feeds back to the

input.

The power dissipated by an input buffer (VIH = VDD –

0.3 V or higher) is estimated as:

PIN = 0.033 mW/MHz

The OR2TxxB 5 V tolerant input buffer feature does not

dissipate additional dc power.

The ac power dissipation from an output or bidirec-

tional is estimated by the following:

POUT = (CL + 8.8 pF) x VDD2 x F Watts

where the unit for CL is farads, and the unit for F is Hz.

As an example of estimating power dissipation,

suppose that a fully utilized OR2T15B has an average

of three outputs for each of the 400 PFUs, that all

20 clock branches are used, that 150 of the 400 PFUs

have FFs clocked at 40 MHz (16 of which are operating

in a synchronous memory mode), and that the PFU

outputs have an average activity factor of 20%.

Twenty inputs, 32 outputs driving 30 pF loads, and

16 bidirectional I/Os driving 50 pF loads are also gen-

erated from the 40 MHz clock with an average activity

factor of 20%. The worst-case (VDD = 3.6 V) power dis-

sipation is estimated as follows:

PPFU = 400 x 3 (0.08 mW/MHz x 20 MHz x 20%)

= 384 mW

PCLK = [0.30 mW/MHz + (0.085 mW/MHz – Branch)

(20 Branches)

+ (0.008 mW/MHz – PFU) (150 PFUs)

+ (0.002 mW/MHz – SMEM_PFU)

(16 SMEM_PFUs)] [40 MHz]

= 129 mW

PIN = 20 x [0.033 mW/MHz x 20 MHz x 20%]

= 3 mW

PTOL = 3.4 mW

+ (0.118 mW/MHz – Branch) (# Branches)

POUT = 30 x [(30 pF + 8.8 pF) x (3.6)2 x 20 MHz

+ (0.008 mW/MHz – PFU) (# PFUs)

+ (0.002 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

For a quick estimate, the worst-case (typical circuit)

OR2T40B clock power ≈ 5.5 mW/MHz.

x 20%]

= 60 mW

PBID = 16 x [(50 pF + 8.8 pF) x (3.6)2 x 20 MHz

x 20%]

= 49 mW

The power dissipated in a PIC is the sum of the power

dissipated in the four I/Os in the PIC. This consists of

TOTAL = 0.72 W

Lattice Semiconductor

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