ORCA Series 2 FPGAs
Data Sheet
November 2006
Pin Information (continued)
Table 19. OR2C04A, OR2C12A, and OR2C/2T15A 84-Pin PLCC Pinout (continued)
Pin 2C04A Pad 2C12A Pad
2C/2T15A
Pad
Function
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PB6A
VSS
PB7A
S PB7D
PB8A
PB9A
E PB9D
PB10A
PB10D
IC DONE
D RESET
PRGM
V PR10A
E PR10D
PR9A
E PR9D
U PR8A
PR7A
D IN PR7D
PR6A
VDD
T PR5A
T VSS
PR4A
C PR4D
N PR3A
PR2A
E PR2D
O PR1A
L PR1D
RD_CFG
E C VDD
VSS
S IS PT10C
PT9D
PT9C
D PT9A
PB10A
VSS
PB11A
PB11D
PB12A
PB13A
PB13D
PB15A
PB18D
DONE
RESET
PRGM
PR18A
PR16A
PR15D
PR13A
PR12A
PR11A
PR11D
PR10A
VDD
PR9A
VSS
PR8A
PR8D
PR7A
PR6A
PR5D
PR4A
PR2A
RD_CFG
VDD
VSS
PT17D
PT15D
PT14D
PT13B
PB11A
VSS
PB12A
PB12D
PB13A
PB14A
PB14D
PB16A
PB20D
DONE
RESET
PRGM
PR20A
PR17A
PR16D
PR14A
PR13A
PR12A
PR12D
PR11A
VDD
PR10A
VSS
PR9A
PR9D
PR8A
PR7A
PR6D
PR5A
PR3A
RD_CFG
VDD
VSS
PT19A
PT16D
PT15D
PT14B
I/O
VSS
I/O-VDD5
I/O
I/O-HDC
I/O-LDC
I/O
I/O-INIT
I/O
DONE
RESET
PRGM
I/O-M0
I/O
I/O-M1
I/O
I/O-M2
I/O-M3
I/O
I/O
VDD
I/O
VSS
I/O
I/O
I/O-CS1
I/O-CS0
I/O
I/O-RD
I/O-WR
RD_CFG
VDD
VSS
I/O-RDY/RCLK
I/O-D7
I/O
I/O-D6
81
PT8A
PT12A
PT13A
I/O-D5
82
PT7D
PT11D
PT12D
I/O
83
PT7A
PT11A
PT12A
I/O-D4
84
PT6A
PT10A
PT11A
I/O-D3
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB
series, but they are connected to VDD5 for the OR2TxxA series.
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Lattice Semiconductor