AD5280BRU200 查看數據表（PDF） - Analog Devices
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AD5280BRU200 Datasheet PDF : 20 Pages
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AD5280/AD5282
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A to be proportional to the input voltage
at A-to-B. Unlike the polarity of VDD–VSS, which must be positive,
voltage across A–B, W–A, and W–B can be at either polarity
provided that VSS is powered by a negative supply.
If ignoring the effect of the wiper resistance for approximation,
connecting A terminal to 5 V and B terminal to ground produces
an output voltage at the wiper-to-B starting at 0 V up to 1 LSB
less than 5 V. Each LSB of voltage is equal to the voltage
applied across A–B divided by the 256 positions of the potenti-
ometer divider. Since AD5280/AD5282 can be supplied by dual
supplies, the general equation defining the output voltage at VW
with respect to ground for any valid input voltage applied to
terminals A and B is:
( ) VW
D
=
D
V
256
A
+
256 – D
256
VB
(3)
For a more accurate calculation, which includes the effect
of wiper resistance, VW can be found as:
( ) ( ) ( ) VW
D
= RWB D
R AB
VA
+
RWA D
R AB
VB
(4)
Operation of the digital potentiometer in the Divider Mode
results in a more accurate operation overtemperature. Unlike
the Rheostat Mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not on the absolute
values; therefore, the temperature drift reduces to 5 ppm/°C.
DIGITAL INTERFACE
2-Wire Serial Bus
The AD5280/AD5282 are controlled via an I2C compatible
serial bus. The RDACs are connected to this bus as slave devices.
Referring to Figures 2 and 3, the first byte of AD5280/AD5282 is
a Slave Address Byte. It has a 7-bit slave address and an R/W bit.
The 5 MSBs are 01011 and the following two bits are determined
by the state of the AD0 and AD1 pins of the device. AD0 and
AD1 allow the user to place up to four of the I2C compatible
devices on one bus.
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 2). The
following byte is the Slave Address Byte which consists of
the 7-bit slave address followed by an R/W bit (this bit
determines whether data will be read from or written to the
slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master will read
from the slave device. On the other hand, if the R/W bit is
low, the master will write to the slave device.
2. A write operation contains an extra Instruction Byte more than
a read operation. Such an Instruction Byte in Write Mode
follows the Slave Address Byte. The MSB of the Instruction
Byte labeled A/B is the RDAC subaddress select. A “low”
selects RDAC1 and a “high” selects RDAC2 for the dual-
channel AD5282. Set A/B to low for the AD5280.
The second MSB, RS, is the midscale reset. A logic high on
this bit moves the wiper of a selected channel to the center
tap where RWA = RWB. This feature effectively writes over
the contents of the register, and thus when taken out of reset
mode, the RDAC will remain at midscale.
The third MSB SD is a shutdown bit. A logic high causes
the selected channel to open circuit at terminal A while
shorting the wiper to terminal B. This operation yields almost
0 Ω in Rheostat Mode or 0 V in Potentiometer Mode. This
SD bit serves the same function as the SHDN pin except
that the SHDN pin reacts to active low. Also, the SHDN
pin affects both channels (AD5282) as opposed to the SD
bit, which only affects the channel that is being written to. It
is important to note that the shutdown operation does not
disturb the contents of the register. When brought out of
shutdown, the previous setting will be applied to the RDAC.
The following two bits are O1 and O2. They are extra pro-
grammable logic outputs that can be used to drive other
digital loads, logic gates, LED drivers, analog switches, and
so on. The three LSBs are Don’t Care (see Figure 2).
3. After acknowledging the Instruction Byte, the last byte in
Write Mode is the Data Byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an Acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 2).
4. In the Read Mode, the Data Byte follows immediately after
the acknowledgment of the Slave Address Byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the Write Mode, where there
are eight data bits followed by an Acknowledge bit). Similarly,
the transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 3).
5. When all data bits have been read or written, a Stop condition
is established by the master. A Stop condition is defined as a
low-to-high transition on the SDA line while SCL is high. In
Write Mode, the master will pull the SDA line high during
the tenth clock pulse to establish a Stop condition, (see
Figure 2). In Read Mode, the master will issue a No Acknowl-
edge for the ninth clock pulse (i.e., the SDA line remains
high). The master will then bring the SDA line low before
the tenth clock pulse, which goes high to establish a Stop
condition (see Figure 3).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the write cycle, each data byte will
update the RDAC output. For example, after the RDAC has
acknowledged its slave address and instruction bytes, the RDAC
output will update after these two bytes. If another byte is writ-
ten to the RDAC while it is still addressed to a specific slave
device with the same instruction, this byte will update the out-
put of the selected slave device. If different instructions are
needed, the Write Mode has to start with a new Slave Address,
Instruction, and Data Byte again. Similarly, a repeated read
function of the RDAC is also allowed.
–12–
REV. 0
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