AD5280BRU200 查看數據表（PDF） - Analog Devices
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AD5280BRU200 Datasheet PDF : 20 Pages
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AD5280/AD5282
However, the digital inputs must also be level shifted to allow
proper operation since the ground is now referenced to the
negative potential. As a result, Figure 9 shows one implementation
with a few transistors and a few resistors. When VIN is below
Q3’s threshold value, Q3 is off, Q1 is off, and Q2 is on. In this
state, VOUT approaches 0 V. When VIN is above 2 V, Q3 is on,
Q1 is on, and Q2 is turned off. In this state, VOUT is pulled
down to VSS. Beware that proper time shifting is also needed for
successful communication with the device.
VDD
+5V
VIN
Q3
0
Q1
0
R2
10k⍀
0
Q2
R3
10k⍀
VOUT
0
–5V
VSS = –5V
Figure 9. Level Shift for Bipolar Potential Operation
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 10; applies to
digital input pins, SDA, SCL, and SHDN.
340⍀
LOGIC
VSS
Figure 10a. ESD Protection of Digital Pins
POWER-UP SEQUENCE
Since there are ESD protection diodes that limit the voltage
compliance at terminals A, B, and W (see Figure 11), it is im-
portant to power VDD/VSS before applying any voltage to
terminals A, B, and W. Otherwise, the diode will be forward
biased such that VDD/VSS will be powered unintentionally and
may affect the rest of the user’s circuit. The ideal power-up
sequence is in the following order: GND, VDD, VSS, digital
inputs, and VA/B/W. The order of powering VA, VB, VW, and
digital inputs is not important as long as they are powered
after VDD/VSS.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths should
have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 µF to 0.1 µF disc or
chip ceramics capacitors. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and filter low frequency
ripple (see Figure 12). Notice the digital ground should also be
joined remotely to the analog ground at one point to minimize
the digital ground bounce.
VDD
C3 +
C1
10F
0.1F
C4 +
C2
10F
0.1F
VSS
AD5280/AD5282
VDD
VSS GND
A, B, W
Figure 12. Power Supply Bypassing
VSS
Figure 10b. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5280/AD5282 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on ter-
minals A, B, and W that exceed VDD or VSS will be clamped by
the internal forward biased diodes (see Figure 11).
VDD
A
W
B
VSS
Figure 11. Maximum Terminal Voltages Set by
VDD and VSS
APPLICATIONS
Bipolar DC or AC Operation from Dual Supplies
The AD5280/AD5282 can be operated from dual supplies
enabling control of ground referenced ac signals or bipolar
operation. The ac signal, as high as VDD/VSS, can be applied
directly across terminals A–B with the output taken from terminal
W. See Figure 13 for a typical circuit connection.
VDD
C
SCLK
MOSI
GND
VDD
SCL
SDA
AD5282
GND
VSS
+5.0V
A1
W1 ؎2.5V p-p
B1
D = 80H
؎5V p-p
A2
W2
B2
–5.0V
Figure 13. Bipolar Operation from Dual Supplies
–14–
REV. 0
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