C8051F002 查看數據表（PDF） - Silicon Laboratories

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C8051F002

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is 0 or the input signal /INT0 is

logic-level one. Setting GATE0 to logic 1 allows the timer to be controlled by the external input signal /INT0,

facilitating pulse width measurements.

TR0 GATE0

0

X

1

0

1

1

1

1

X = Don’t Care

/INT0

X

X

0

1

Counter/Timer

Disabled

Enabled

Disabled

Enabled

Setting TR0 does not reset the timer register. The timer register should be initialized to the desired value before

enabling the timer.

TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer

1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0.

SYSCLK

Figure 19.1. T0 Mode 0 Block Diagram

12

0

CKCON

TTT

210

MMM

TMOD

GCT T GCT T

A / 11A / 00

T

E

T MM

T

E

T MM

1 1100010

1

0

1

T0

Crossbar

TR0

TCLK

TL0

(5 bits)

TH0

(8 bits)

GATE0

/INT0 Crossbar

TF1

TR1

TF0

Interrupt

TR0

IE1

IT1

IE0

IT0

19.1.2. Mode 1: 16-bit Counter/Timer

Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers

are enabled and configured in Mode 1 in the same manner as for Mode 0.

139

Rev. 1.7

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