C8051F002 查看數據表（PDF） - Silicon Laboratories

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C8051F002

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

16.6.5. Status Register

The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus. There are 28

possible SMBus states, each with a corresponding unique status code. The five most significant bits of the status

code vary while the three least-significant bits of a valid status code are fixed at zero when SI = 1. Therefore, all

possible status codes are multiples of eight. This facilitates the use of status codes in software as an index used to

branch to appropriate service routines (allowing 8 bytes of code to service the state or jump to a more extensive

service routine).

For the purposes of user software, the contents of the SMB0STA register is only defined when the SI flag is logic 1.

Software should never write to the SMB0STA register. Doing so will yield indeterminate results. The 28 SMBus

states, along with their corresponding status codes, are given in Table 16.1.

Figure 16.8. SMB0STA: SMBus Status Register

R/W

STA7

Bit7

R/W

STA6

Bit6

R/W

STA5

Bit5

R/W

STA4

Bit4

R/W

STA3

Bit3

R/W

STA2

Bit2

R/W

STA1

Bit1

R/W

STA0

Bit0

Reset Value

11111000

SFR Address:

0xC1

Bits7-3: STA7-STA3: SMBus Status Code.

These bits contain the SMBus Status Code. There are 28 possible status codes. Each

status code corresponds to a single SMBus state. A valid status code is present in

SMB0STA when the SI flag (SMB0CN.3) is set. The content of SMB0STA is not defined

when the SI flag is logic 0. Writing to the SMB0STA register at any time will yield

indeterminate results.

Bits2-0: STA2-STA0: The three least significant bits of SMB0STA are always read as logic 0 when

the SI flag is logic 1.

121

Rev. 1.7

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