C8051F002 查看數據表（PDF） - Silicon Laboratories

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C8051F002

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)

Timer 0 and Timer 1 behave differently in Mode 3. Timer 0 is configured as two separate 8-bit counter/timers held

in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD:

TR0, C/T0, GATE0 and TF0. It can use either the system clock or an external input signal as its timebase. The

TH0 register is restricted to a timer function sourced by the system clock. TH0 is enabled using the Timer 1 run

control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt.

Timer 1 is inactive in Mode 3, so with Timer 0 in Mode 3, Timer 1 can be turned off and on by switching it into and

out of its Mode 3. When Timer 0 is in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked

by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used for

baud rate generation. Refer to Section 18 (UART) for information on configuring Timer 1 for baud rate generation.

SYSCLK

Figure 19.3. T0 Mode 3 Block Diagram

CKCON

TTT

210

MMM

TR1

12

0

1

0

TMOD

GCT T GCT T

A / 11A / 00

T

T

E T MM E T MM

1 1100010

C/T0

TH0

(8 bits)

1

T0 Crossbar

TR0

TL0

(8 bits)

GATE0

/INT0 Crossbar

TF1

Interrupt

TR1

TF0

Interrupt

TR0

IE1

IT1

IE0

IT0

141

Rev. 1.7

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