C8051F002 查看數據表（PDF） - Silicon Laboratories

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C8051F002

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 19.14. T2CON: Timer 2 Control Register

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable) 0xC8

Bit7:

TF2: Timer 2 Overflow Flag.

Set by hardware when Timer 2 overflows from 0xFFFF to 0x0000 or reload value. When

the Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2

interrupt service routine. This bit is not automatically cleared by hardware and must be

cleared by software. TF2 will not be set when RCLK and/or TCLK are logic 1.

Bit6:

EXF2: Timer 2 External Flag.

Set by hardware when either a capture or reload is caused by a high-to-low transition on

the T2EX input pin and EXEN2 is logic 1. When the Timer 2 interrupt is enabled, setting

this bit causes the CPU to vector to the Timer 2 Interrupt service routine. This bit is not

automatically cleared by hardware and must be cleared by software.

Bit5:

RCLK: Receive Clock Flag.

Selects which timer is used for the UART’s receive clock in modes 1 or 3.

0: Timer 1 overflows used for receive clock.

1: Timer 2 overflows used for receive clock.

Bit4:

TCLK: Transmit Clock Flag.

Selects which timer is used for the UART’s transmit clock in modes 1 or 3.

0: Timer 1 overflows used for transmit clock.

1: Timer 2 overflows used for transmit clock.

Bit3:

EXEN2: Timer 2 External Enable.

Enables high-to-low transitions on T2EX to trigger captures or reloads when Timer 2 is not

operating in Baud Rate Generator mode.

0: High-to-low transitions on T2EX ignored.

1: High-to-low transitions on T2EX cause a capture or reload.

Bit2:

TR2: Timer 2 Run Control.

This bit enables/disables Timer 2.

0: Timer 2 disabled.

1: Timer 2 enabled.

Bit1:

C/T2: Counter/Timer Select.

0: Timer Function: Timer 2 incremented by clock defined by T2M (CKCON.5).

1: Counter Function: Timer 2 incremented by high-to-low transitions on external input pin

(T2).

Bit0:

CP/RL2: Capture/Reload Select.

This bit selects whether Timer 2 functions in capture or auto-reload mode. EXEN2 must

be logic 1 for high-to-low transitions on T2EX to be recognized and used to trigger

captures or reloads. If RCLK or TCLK is set, this bit is ignored and Timer 2 will function

in auto-reload mode.

0: Auto-reload on Timer 2 overflow or high-to-low transition at T2EX (EXEN2 = 1).

1: Capture on high-to-low transition at T2EX (EXEN2 = 1).

Rev. 1.7

150

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