C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

Table 12.4. Interrupt Summary (Continued)

Interrupt Source

Interrupt

Vector

Priority

Order

Pending Flag

Enable

Flag

Priority

Control

Comparator 1

Comparator 2

Timer 3

ADC0 End of

Conversion

Timer 4

ADC2 Window

Comparator

ADC2 End of

Conversion

CAN Interrupt

UART1

0x005B 11

0x0063 12

0x0073 14

0x007B 15

0x0083 16

0x0093 17

0x008B 18

0x009B 19

0x00A3 20

CP1FIF/CP1RIF

(CPT1CN.4/.5)

2

CP1IE

(EIE1.5)

PCP1

(EIP1.5)

CP2FIF/CP2RIF

(CPT2CN.4/.5)

3

CP2IE

(EIE1.6)

PCP2

(EIP1.6)

TF3 (TMR3CN.7)

1

ET3

(EIE2.0)

PT3

(EIP2.0)

ADC0INT

(ADC0CN.5)

Y

0

EADC0

(EIE2.1)

PADC0

(EIP2.1)

TF4 (TMR4CN.7)

2

ET4

(EIE2.2)

PT4

(EIP2.2)

AD2WINT

(ADC2CN.0)

2

EWADC2

(EIE2.3)

PWADC2

(EIP2.3)

ADC2INT

(ADC1CN.5)

2

EADC1

(EIE2.4)

PADC1

(EIP2.4)

CAN0CN.7

Y

1

ECAN0

(EIE2.5)

PCAN0

(EIP2.5)

RI1 (SCON1.0)

TI1 (SCON1.1)

1

ES1

(EIE2.6)

PS1

(EIP2.6)

Rev. 1.5

155

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