C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 12.14. EIE2: Extended Interrupt Enable 2

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

-

ES1 ECAN0 EADC2 EWADC2 ET4 EADC0

ET3 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xE7

SFR Page: All Pages

Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

Reserved

ES1: Enable UART1 Interrupt.

This bit sets the masking of the UART1 interrupt.

0: Disable UART1 interrupt.

1: Enable UART1 interrupt.

ECAN0: Enable CAN Controller Interrupt.

This bit sets the masking of the CAN Controller Interrupt.

0: Disable CAN Controller Interrupt.

1: Enable interrupt requests generated by the CAN Controller.

EADC2: Enable ADC2 End Of Conversion Interrupt (C8051F040/1/2/3 only).

This bit sets the masking of the ADC2 End of Conversion interrupt.

0: Disable ADC2 End of Conversion interrupt.

1: Enable interrupt requests generated by the ADC2 End of Conversion Interrupt.

EWADC2: Enable Window Comparison ADC2 Interrupt (C8051F040/1/2/3 only).

This bit sets the masking of ADC2 Window Comparison interrupt.

0: Disable ADC2 Window Comparison Interrupt.

1: Enable Interrupt requests generated by ADC2 Window Comparisons.

ET4: Enable Timer 4 Interrupt

This bit sets the masking of the Timer 4 interrupt.

0: Disable Timer 4 interrupt.

1: Enable interrupt requests generated by the TF4 flag.

EADC0: Enable ADC0 End of Conversion Interrupt.

This bit sets the masking of the ADC0 End of Conversion Interrupt.

0: Disable ADC0 Conversion Interrupt.

1: Enable interrupt requests generated by the ADC0 Conversion Interrupt.

ET3: Enable Timer 3 Interrupt.

This bit sets the masking of the Timer 3 interrupt.

0: Disable all Timer 3 interrupts.

1: Enable interrupt requests generated by the TF3 flag.

160

Rev. 1.5

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