C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 17.6. P0MDOUT: Port0 Output Mode

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xA4

SFR Page: F

Bits7-0: P0MDOUT.[7:0]: Port0 Output Mode Bits.

0: Port Pin output mode is configured as Open-Drain.

1: Port Pin output mode is configured as Push-Pull.

Note:

SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are

always configured as Open-Drain when they appear on Port pins.

SFR Definition 17.7. P1: Port1 Data

R/W

P1.7

Bit7

R/W

P1.6

Bit6

R/W

P1.5

Bit5

R/W

P1.4

Bit4

R/W

P1.3

Bit3

R/W

P1.2

Bit2

R/W

P1.1

Bit1

R/W

Reset Value

P1.0 11111111

Bit0

Bit

Addressable

SFR Address: 0x90

SFR Page: All Pages

Bits7-0:

P1.[7:0]: Port1 Output Latch Bits.

(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)

0: Logic Low Output.

1: Logic High Output (open if corresponding P1MDOUT.n bit = 0).

(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).

0: P1.n pin is logic low.

1: P1.n pin is logic high.

Notes:

1.

2.

P1.[7:0] can be configured as inputs to ADC1 as AIN1.[7:0], in which case they are ‘skipped’

by the Crossbar assignment process and their digital input paths are disabled, depending on

P1MDIN (See SFR Definition 17.8). Note that in analog mode, the output mode of the pin is

determined by the Port 1 latch and P1MDOUT (SFR Definition 17.9). See Section “7. 8-Bit

ADC (ADC2, C8051F040/1/2/3 Only)” on page 91 for more information about ADC2.

P1.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-mul-

tiplexed mode). See Section “16. External Data Memory Interface and On-Chip XRAM”

on page 187 for more information about the External Memory Interface.

216

Rev. 1.5

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