C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 17.10. P2: Port2 Data

R/W

P2.7

Bit7

R/W

P2.6

Bit6

R/W

P2.5

Bit5

R/W

P2.4

Bit4

R/W

P2.3

Bit3

R/W

P2.2

Bit2

R/W

P2.1

Bit1

R/W

Reset Value

P2.0 11111111

Bit0

Bit

Addessable

SFR Address: 0xA0

SFR Page: All Pages

Bits7-0:

P2.[7:0]: Port2 Output Latch Bits.

(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)

0: Logic Low Output.

1: Logic High Output (open if corresponding P2MDOUT.n bit = 0).

(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).

0: P2.n pin is logic low.

1: P2.n pin is logic high.

Note:

P2.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multi-

plexed mode, or as Address[7:0] in Non-multiplexed mode). See Section “16. External

Data Memory Interface and On-Chip XRAM” on page 187 for more information about the

External Memory Interface.

SFR Definition 17.11. P2MDIN: Port2 Input Mode

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xAE

SFR Page: F

Bits7-0:

P1MDIN.[7:0]: Port 2 Input Mode Bits.

0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from

the Port bit will always return ‘0’). The weak pullup on the pin is disabled.

1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic

level at the Pin. The state of the weak pullup is determined by the WEAKPUD bit (XBR2.7,

see SFR Definition 17.3).

218

Rev. 1.5

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