C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 23.9. TMRnCF: Timer n Configuration

R/W

R/W

-

-

-

TnM1 TnM0

Bit7

Bit6

Bit5

Bit4

Bit3

SFR Address: TMR2CF:0xC9;TMR3CF:0xC9;TMR4CF:0xC9

SFR Page TMR2CF: page 0;TMR3CF: page 1;TMR4CF: page 2

R/W

TOGn

Bit2

R/W

TnOE

Bit1

R/W

DCEN

Bit0

Reset Value

00000000

Bit

Addressable

Bit7-5:

Bit4-3:

Bit2:

Bit1:

Bit0:

Reserved.

TnM1 and TnM0: Timer Clock Mode Select Bits.

Bits used to select the Timer clock source. The sources can be the System Clock

(SYSCLK), SYSCLK divided by 2 or 12, or an external clock signal routed to Tn (port pin)

divided by 8. Clock source is selected as follows:

00: SYSCLK/12

01: SYSCLK

10: EXTERNAL CLOCK/8

11: SYSCLK/2

TOGn: Toggle output state bit.

When timer is used to toggle a port pin, this bit can be used to read the state of the output, or

can be written to in order to force the state of the output.

TnOE: Timer output enable bit.

This bit enables the timer to output a 50% duty cycle output to the timer’s assigned external

port pin.

NOTE: A timer is configured for Square Wave Output as follows:

CP/RLn = 0

C/Tn = 0

TnOE = 1

Load RCAPnH:RCAPnL (See Section “Equation 23.1. Square Wave Frequency” on

page 298).

Configure Port Pin for output (See Section “17. Port Input/Output” on page 203).

0: Output of toggle mode not available at Timers’ assigned port pin.

1: Output of toggle mode available at Timers’ assigned port pin.

DCEN: Decrement Enable Bit.

This bit enables the timer to count up or down as determined by the state of TnEX.

0: Timer will count up, regardless of the state of TnEX.

1: Timer will count up or down depending on the state of TnEX as follows:

if TnEX = 0, the timer counts DOWN

if TnEX = 1, the timer counts UP.

300

Rev. 1.5

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