C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

24.2.1. Edge-triggered Capture Mode

In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/

timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and

PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-

tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),

or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)

in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn

bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and

must be cleared by software.

Note: The signal at the CEXn pin must be logic high or low for at least two system clock cycles in order for

it to be recognized as valid by the hardware.

Port I/O

PCA0CPMn

P ECCMT P E

WCA A AOWC

MOP P TGMC

1 MPN n n n F

6nnn

n

n

PCA Interrupt

PCA0CN

CCCCCCCC

FRCCCCCC

FFFFFF

543210

Crossbar CEXn

0

1

0

1

PCA0CPLn PCA0CPHn

Capture

PCA

Timebase

PCA0L

PCA0H

Figure 24.4. PCA Capture Mode Diagram

306

Rev. 1.5

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