C8051F38B-GMR 查看數據表（PDF） - Silicon Laboratories

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C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

21.3. USB Register Access

The USB0 controller registers listed in Table 21.2 are accessed through two SFRs: USB0 Address

(USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted

by reads/writes of the USB0DAT register. See Figure 21.2.

Endpoint control/status registers are accessed by first writing the USB register INDEX with the target end-

point number. Once the target endpoint number is written to the INDEX register, the control/status registers

associated with the target endpoint may be accessed. See the “Indexed Registers” section of Table 21.2

for a list of endpoint control/status registers.

Important Note: The USB clock must be active when accessing USB registers.

8051

SFRs

USB0DAT

USB0ADR

USB Controller

Interrupt

Registers

FIFO

Access

Common

Registers

Index

Register

Endpoint0 Control/

Status Registers

Endpoint1 Control/

Status Registers

Endpoint2 Control/

Status Registers

Endpoint3 Control/

Status Registers

Figure 21.2. USB0 Register Access Scheme

Rev. 1.4

175

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