C8051F38B-GMR 查看數據表（PDF） - Silicon Laboratories

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C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

SFR Definition 21.2. USB0ADR: USB0 Indirect Address

Bit

7

6

5

4

3

2

1

0

Name BUSY AUTORD

USBADDR[5:0]

Type R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

SFR Address = 0x96; SFR Page = All Pages

Bit

Name

Description

Write

Read

7

BUSY

USB0 Register Read

0: No effect.

0: USB0DAT register data

Busy Flag.

1: A USB0 indirect regis- is valid.

This bit is used during ter read is initiated at the

indirect USB0 register address specified by the

accesses.

USBADDR bits.

1: USB0 is busy access-

ing an indirect register;

USB0DAT register data is

invalid.

6

AUTORD USB0 Register Auto-read Flag.

This bit is used for block FIFO reads.

0: BUSY must be written manually for each USB0 indirect register read.

1: The next indirect register read will automatically be initiated when software

reads USB0DAT (USBADDR bits will not be changed).

5:0 USBADDR[5:0] USB0 Indirect Register Address Bits.

These bits hold a 6-bit address used to indirectly access the USB0 core registers.

Table 21.2 lists the USB0 core registers and their indirect addresses. Reads and

writes to USB0DAT will target the register indicated by the USBADDR bits.

176

Rev. 1.4

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