CRD44800-ST-FB 查看數據表（PDF） - Cirrus Logic

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CRD44800-ST-FB

6-Channel Digital Amplifier Controller

Cirrus Logic 

CS44600

• Digital volume control with soft ramp.

• Individual channel volume gain, attenuation and mute capability; +24 to -127 dB in 0.25 dB steps.

• Master volume attenuation; +24 to -127 dB in 0.25 dB steps.

• Peak Detect and Volume Limiter with programmable attack and release rates.

• Signal-clipping interrupt indicator.

Additional Features

• Contains a two-stage digital output filter for speaker impedance compensation.

• Provides 7 programmable GPIO pins with interrupt generation for easily interfacing to a variety of com-

monly available power state parts. Interrupts can be masked.

• Selectable over-sample rate for increased audio bandwidth.

• Power supply clock output, PS_SYNC, with programmable divider

DAI_MCLK

DAI_LRCK

DAI_SCLK

DAI_SDINx

XTO

XTI

SYS_CLK

1, 1.5, 2,

3, 4, 6, 8

Ratio Detect

Digital Audio

Input Port

FsIn FsOut

128Fs

Master

Volume

Channel

Volume

Σ

LIMITER

De-

Emphasis

SRC

2-pole Load

Compensation

Filter

PEAK

DETECT

mute

SRC_MCLK (128Fs)

MOD_MCLK

Over Sample

(OSRATE)

x2

Multibit

Σ∆

Modulator

PSR

Feedback

PWM Engine

XTAL /

CLKIN

2.25

1,1.5,

2,4

Clock Control

PWM_MCLK

1,2,4,8

Over Sample

(OSRATE)

AM Freq. Hop

(AM_FREQ_HOP)

Figure 13. CS44600 Data Flow Diagram (Single Channel Shown)

Delay

Delay

4.3 Clock Generation

The sources for internal clock generation for the PWM processing are as follows:

• FsIn Domain:

– DAI_MCLK, minimum 128Fs

• FsOut Domain:

– XTI/XTO (Fundamental or 3rd overtone crystal), or

– Clock signal on XTI (VDX is used to set logic voltage level)

PWM_OUT+

PWM_OUT-

DS633F1

23

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