CRD44800-ST-FB 查看數據表（PDF） - Cirrus Logic

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CRD44800-ST-FB

6-Channel Digital Amplifier Controller

Cirrus Logic 

4.3.1 FsIn Domain Clocking

Common DAI_MCLK frequencies and sample rates are shown in Table 1.

Mode

Sample

(sample-rate range) Rate

(kHz)

DAI_MCLK/LRCK Ratio −>

Single Speed

32

(4 to 50 kHz)

44.1

48

DAI_MCLK/LRCK Ratio −>

Double Speed

64

(50 to 100 kHz)

88.2

96

DAI_MCLK/LRCK Ratio −>

Quad Speed

176.4

(100 to 200 kHz)

192

DAI_MCLK (MHz)

256x

8.1920

11.2896

12.2880

384x

12.2880

16.9344

18.4320

512x

16.3840

22.5792

24.5760

128x

8.1920

11.2896

12.2880

64x

n/a

n/a

192x

12.2880

16.9344

18.4320

96x

n/a

n/a

256x

16.3840

22.5792

24.5760

128x

22.5792

24.5760

Table 1. Common DAI_MCLK Frequencies

768x

24.5760

33.8688

36.8640

384x

24.5760

33.8688

36.8640

192x

33.8688

36.8640

CS44600

1024x

32.7680

45.1584

49.1520

512x

32.7680

45.1584

49.1520

256x

45.1584

49.1520

4.3.2

FsOut Domain Clocking

To ensure the highest quality conversion of PWM signals, the CS44600 is capable of operating from a

fundamental mode or 3rd overtone crystal, or a clock signal attached to XTI, at a frequency of 24.576 MHz

to 54 MHz. If XTI is being directly driven by a clock signal, XTO can be left floating or tied to ground

through a pull-down resistor and the internal oscillator should be powered down using the PDN_XTAL bit

in register 02h.

XTI

Y1

C1

XTO

C2

Figure 14. Fundamental Mode Crystal Configuration

24

DS633F1

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