CRD44800-ST-FB 查看數據表（PDF） - Cirrus Logic

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CRD44800-ST-FB

6-Channel Digital Amplifier Controller

Cirrus Logic 

CS44600

4.4.1.1 I²S Data Format

For I²S, data is received most significant bit first, one DAI_SCLK delay after the transition of DAI_LRCK,

and is valid on the rising edge of DAI_SCLK. For the I²S format, the left channel data is presented when

DAI_LRCK is low; the right channel data is presented when DAI_LRCK is high.

DAI_LRCK

DAI_SCLK

DAI_SDINx

Left Channel

Right Channel

MSB -1 -2 -3 -4 -5

+5 +4 +3 +2 +1 LSB

MSB -1 -2 -3 -4

+5 +4 +3 +2 +1 LSB

I²S Mode, Data Valid on Rising Edge of DAI_SCLK

Bits/Sample

SCLK Rates

16

32, 48, 64, 128, 256 Fs

18 to 24

48, 64, 128, 256 Fs

Figure 17. I²S Serial Audio Formats

4.4.1.2 Left-Justified Data Format

For left-justified format, data is received most significant bit first on the first DAI_SCLK after a DAI_LRCK

transition and is valid on the rising edge of DAI_SCLK. For the left-justified format, the left channel data

is presented when DAI_LRCK is high and the right channel data is presented when DAI_LRCK is low.

DAI_LRCK

DAI_SCLK

DAI_SDINx

Left Channel

Right Channel

MSB -1 -2 -3 -4 -5

+5 +4 +3 +2 +1 LSB

MSB -1 -2 -3 -4

+5 +4 +3 +2 +1 LSB

Left-Justified Mode, Data Valid on Rising Edge of DAI_SCLK

Bits/Sample

SCLK Rate(s)

16

32, 48, 64, 128, 256 Fs

18 to 24

48, 64, 128, 256 Fs

Figure 18. Left-Justified Serial Audio Formats

DS633F1

27

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