CS8952(2001) 查看數據表（PDF） - Cirrus Logic
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CS8952 Datasheet PDF : 82 Pages
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CS8952
6.9 Interrupt Mask Register - Address 10h
15
CIM Link
Unstable
7
Reset
Complete
14
Link Status
Change
13
12
Descrambler Premature End
Lock Change
Error
11
DCR
Rollover
6
Jabber
Detect
5
Auto-Neg
Complete
4
Parallel
Detection Fault
3
Parallel
Fail
10
FCCR
Rollover
2
Remote
Fault
9
RECR
Rollover
1
Page
Received
8
Remote
Loopback
Fault
0
Reserved
This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as
an enable to the interrupt. Thus, when set, the event will cause the MII_IRQ pin to be asserted. When
clear, the event will not affect the MII_IRQ pin, but the status will still be reported via the Interrupt Sta-
tus Register (address 11h).
BIT
NAME
TYPE
RESET
15 CIM Link Unstable Read/Write 0
14 Link Status Change Read Write 1
13 Descrambler Lock Read/Write 0
Change
12 Premature End
Error
Read/Write 0
DESCRIPTION
When set, an interrupt will be generated if an unsta-
ble link condition is detected by the Carrier Integrity
Monitor function.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated each time
the CS8952 detects a change in the link status.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated each time
the 100BASE-TX receive descrambler loses or
regains synchronization with the far-end.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when two
consecutive IDLES are detected in a 100BASE-TX
frame without the ESD sequence.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
42
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
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