CS8952(2001) 查看數據表（PDF） - Cirrus Logic
零件编号
产品描述 (功能)
生产厂家
CS8952 Datasheet PDF : 82 Pages
| |||
CS8952
BIT
NAME
11 DCR Rollover
TYPE
RESET
Read/Write 0
10 FCCR Rollover Read/Write 0
9
RECR Rollover Read/Write 0
8
Remote Loopback Read/Write 0
Fault
7
Reset Complete Read/Write 1
6
Jabber Detect
Read/Write 0
DESCRIPTION
When set, an interrupt will be generated if the MSB in
the DCR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the MSB in
the FCCR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the MSB in
the RECR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the elastic
buffer in the PMA is under-run or over-run during
Remote Loopback. This should not occur for normal
length 802.3 frames.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated once the
digital and analog sections have been reset, and a
calibration cycle has been performed.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when a Jab-
ber condition is detected by the 10BASE-T MAU.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
43
Share Link: 