MT90866 查看數據表（PDF） - Zarlink Semiconductor Inc

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MT90866

Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch

Zarlink Semiconductor Inc 

MT90866

Data Sheet

LREF0-7

(1.544 MHz)

NREFo

(8 KHz)

tROD

tR8KO15L

trREF

tR8KOP

tfREF

tR8KO15H

Figure 32 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register

AC Electrical Characteristics† - Local Frame Pulse and Clock Timing, ST_CKo = 4.096MHz

Characteristic

Sym.

Min. Typ.‡ Max. Units

1 Local Frame Boundary Offset1

tLFBOS

∆

17.5+∆ ns

2 ST_FPo0/1 Width

3 ST_FPo0/1 Output Delay from Falling edge

of ST_FPo0/1 to falling edge of ST_CKo0/1

tFPW4

244-∆ 244 244+∆

ns

tFODF4 122-∆/2

122+∆/2 ns

4 ST_FPo 0/1Output Delay from Falling edge

of ST_CKo0/1 to rising edge of ST_FPo0/1

tFODR4 122-∆/2

122+∆/2 ns

5 ST_CKo0/1 Clock Period

tCP4

244-∆ 244 244+∆ ns

6 ST_CKo0/1 Clock Pulse Width High

tCH4

122-∆/2

122+∆/2 ns

7 ST_CKo0/1 Clock Pulse Width Low

tCL4

122-∆/2

122+∆/2 ns

8 ST_CKo0/1 Clock Rise/Fall Time

trC4o, tC4o

14

ns

† Characteristics are over recommended operating conditions unless otherwise stated.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Note 1: No jitter presented on input reference clock.

Notes

CL=30pF

Backplane Frame Boundary

ST_FPo0/1

ST_CKo0/1

(4.096 MHz)

tFPW4

tFODF4

tCP4

tCH4

Local Output Frame Boundary

tLFBOS

tFODR4

tCL4

tfC4o

trC4o

Figure 33 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096 MHz

73

Zarlink Semiconductor Inc.

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