PIC12F1822T-I/SL 查看數據表（PDF） - Microchip Technology
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PIC12F1822T-I/SL Datasheet PDF : 398 Pages
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PIC12F/LF1822/16F/LF1823
23.3 PWM Overview
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
Figure 23-3 shows a typical waveform of the PWM
signal.
23.3.1 STANDARD PWM OPERATION
The standard PWM mode generates a Pulse-Width
modulation (PWM) signal on the CCP1 pin with up to 10
bits of resolution. The period, duty cycle, and resolution
are controlled by the following registers:
• PR2 registers
• T2CON registers
• CCPR1L registers
• CCP1CON registers
Figure 23-4 shows a simplified block diagram of PWM
operation.
Note 1: The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCP1 pin.
2: Clearing the CCP1CON register will
relinquish control of the CCP1 pin.
FIGURE 23-3:
Period
CCP1 PWM OUTPUT
SIGNAL
Pulse Width
TMR2 = 0
TMR2 = PR2
TMR2 = CCPR1H:CCP1CON<5:4>
FIGURE 23-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
CCPR1L
CCP1CON<5:4>
CCPR1H(2) (Slave)
Comparator
RQ
CCP1
TMR2
(1)
S
TRIS
Comparator
PR2
Clear Timer,
toggle CCP1 pin and
latch duty cycle
Note 1:
2:
The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base.
In PWM mode, CCPR1H is a read-only register.
DS41413A-page 204
Preliminary
2010 Microchip Technology Inc.
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