PIC16F688
FIGURE 3-9:
FSCM TIMING DIAGRAM
Sample Clock
System
Clock
Output
Clock Monitor Output
(Q)
OSCFIF
Oscillator
Failure
Failure
Detected
Note:
Test
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets(1)
CONFIG(2)
CPD
CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
—
—
INTCON
GIE
PEIE T0IE
INTE RAIE
T0IF
INTF
RAIF 0000 000x 0000 000x
OSCCON
—
IRCF2 IRCF1 IRCF0 OSTS HTS
LTS
SCS -110 x000 -110 x000
OSCTUNE
—
—
—
TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
PIE1
EEIE ADIE RCIE
C2IE
C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
PIR1
EEIF
ADIF RCIF
C2IF
C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
Legend:
Note 1:
2:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (CONFIG) for operation of all register bits.
DS41203D-page 32
© 2007 Microchip Technology Inc.