PIC16LC717T-I/SO 查看數據表（PDF） - Microchip Technology

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PIC16LC717T-I/SO

18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D

Microchip Technology 

PIC16C717/770/771

TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: Value on all

POR, other resets

BOR

(2)

Bank 2

100h(3) INDF

101h

TMR0

102h(3) PCL

103h(3) STATUS

104h(3) FSR

105h

—

106h

PORTB

107h

—

108h

—

109h

—

10Ah(1,3) PCLATH

10Bh(3) INTCON

10Ch PMDATL

10Dh PMADRL

10Eh

PMDATH

10Fh

PMADRH

110h-

11Fh

—

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module’s register

Program Counter's (PC) Least Significant Byte

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect data memory address pointer

Unimplemented

PORTB Data Latch when written: PORTB pins when read

Unimplemented

Unimplemented

Unimplemented

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

Program memory read data low

Program memory read address low

—

—

Program memory read data high

—

—

—

—

Program memory read address high

Unimplemented

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

—

xxxx xx00

—

—

—

—

uuuu uu00

—

—

—

---0 0000 ---0 0000

0000 000x 0000 000u

xxxx xxxx

xxxx xxxx

--xx xxxx

---- xxxx

uuuu uuuu

uuuu uuuu

--uu uuuu

---- uuuu

—

—

Bank 3

180h(3) INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

181h OPTION_REG RBPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111 1111 1111

182h(3) PCL

Program Counter's (PC) Least Significant Byte

0000 0000 0000 0000

183h(3) STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

184h(3) FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

185h

—

Unimplemented

—

—

186h

TRISB

PORTB Data Direction Register

1111 1111 1111 1111

187h

—

Unimplemented

—

—

188h

—

Unimplemented

—

—

189h

—

Unimplemented

—

—

18Ah(1,3) PCLATH

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

18Bh(3) INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF 0000 000x 0000 000u

18Ch

PMCON1

Reserved

—

—

—

—

—

—

RD

1--- ---0

1--- ---0

18Dh-

18Fh

—

Unimplemented

—

—

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

3: These registers can be addressed from any bank.

© 1999 Microchip Technology Inc.

Advanced Information

DS41120A-page 15

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