PIC16LC717T-I/SO 查看數據表（PDF） - Microchip Technology
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PIC16LC717T-I/SO Datasheet PDF : 200 Pages
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PIC16C717/770/771
2.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the
peripheral interrupts.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-5: PERIPHERAL INTERRUPT REGISTER 1 (PIR1: 0Ch)
U-0
R/W-0
U-0
—
ADIF
—
bit7
U-0
R/W-0
—
SSPIF
bit 7: Unimplemented: Read as ‘0’.
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-4: Unimplemented: Read as ‘0’.
bit 3:
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the
interrupt service routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I2C Slave / Master
A transmission/reception has taken place.
I2C Master
The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).
0 = No SSP interrupt condition has occurred.
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
DS41120A-page 20
Advanced Information
© 1999 Microchip Technology Inc.
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