ST7FMC1M2T3 查看數據表（PDF） - STMicroelectronics

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ST7FMC1M2T3

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

MOTOR CONTROLLER (Cont’d)

10.6.6.5 Demagnetization (D) Event

At the end of the demagnetization phase, current

no longer goes through the free-wheeling diodes.

The voltage on the non-excited winding terminal

goes from one of the power rail voltages to the

common star connection voltage plus the BEMF

voltage. In some cases (if the BEMF voltage is

positive and the free-wheeling diodes are at

ground for example) this end of demagnetization

can be seen as a voltage edge on the selected

MCIx input and it is called a hardware demagneti-

zation event DH. See Table 30.

The D event filter can be used to select the

number of consecutive D events needed to gener-

ate the DH event.

If enabled by the HDM bit in the MCRB register,

the current value of the MTIM timer is captured in

register MDREG when this event occurs in order

to be able to simulate the demagnetization phase

for the next steps.

When enabled by the SDM bit in the MCRB regis-

ter, demagnetization can also be simulated by

comparing the MTIM timer with the MDREG regis-

ter. This kind of demagnetization is called simulat-

ed demagnetization DS.

If the HDM and SDM bits are both set, the first

event that occurs, triggers a demagnetization

event. For this to work correctly, a DS event must

Figure 81. D Event Generation Mechanism

not precede a DH event because the latter could

be detected as a Z event.

Simulated demagnetization can also be always

used if the HDM bit is reset and the SDM bit is set.

This mode works as a programmable masking

time between the CH and Z events. To drive the

motor securely, the masking time must be always

greater than the real demagnetization time in order

to avoid a spurious Z event.

When an event occurs, (either DH or DS) the DI bit

in the MISR register is set and an interrupt request

is generated if the DIM bit of register MIMR is set.

Caution 1: Due to the alternate automatic capture

and compare of the MTIM timer with MDREG reg-

ister by DH and DS events, the MDREG register

should be manipulated with special care.

Caution 2: Due to the event generation protection

in the MZREG, MCOMP and MDREG registers for

Soft Event generation ( See “Built-in Checks and

Controls for simulated events” on page 175.), the

value written in the MDREG register in soft demag-

netisation mode (SDM=1) is checked by hardware

after the C event. If this value is less than or equal

to the MTIM counter value at this moment, the

Software demagnetisation event is generated im-

mediately and the MTIM current value overwrites

the value in the MDREG register to be able to re-

use the right demagnetisation time for another

simulated event generation.

DS,H

C

Sample 2

SPLG bit 1

MCRC

Register

DS

DH

HDM bit

SDM bit

To Z event detection

or

MTIM [8-bit Up Counter] §

8

DH

MDREG [Dn]§

CPBn bit* HDMn bit*

MCRB Register

SR bit

MCRA Register

MCRB Register Compare

SDM* bit

MDFR Register

DWF[3:0]

DWF[3:0]

DEF[3:0]

DS

MDFR Register

DH

D

F(x)

D = DH & HDM bit + DS & SDM bit

§ Register updated on R event

To interrupt generator

* = Preload register, changes taken into account at next C event

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