ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 82. Z Event Generation
MCRB Register MPOL Register MCRA Register
DS,H
CS,H
Sample
SPLG bit
DS[3:0]
bits
ZS
ZH
SZ bit
HZ bit
CPBn bit*
ZVD bit
MPOL Register
REO bit
PZ bit
or or or
2
MCRC Register
1
HZ bit
To D detection
Z = ZH& HZ bit+ ZS & SZ bit
ZH
F(x)
MTIM [8-bit Up Counter] (MSB)§
8
ZH
MZREG [Zn]§
MCRC Register
SZ bit
ZWF[3:0]
ZEF[3:0]
MZFR register
Compare
MZFR register
ZWF[3:0]
ZS
Z
To interrupt generator
§ Register updated on R event
* = Preload register, changes taken into account at next C event
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