STA321MPL 查看數據表（PDF） - STMicroelectronics

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STA321MPL

Scalable digital microphone processor

STMicroelectronics 

STA321MP

Registers

7.2.38 Channel 7 and 8 output timing (0x36)

D7

D6

D5

D4

D3

D2

D1

D0

C8OT2

1

C8OT1

1

C8OT0

1

C7OT2

0

C7OT1

1

C7OT0

1

The centering of the individual channel PWM output periods can be adjusted by the output

timing registers. PWM slot settings can be chosen to ensure that pulse transitions do not

occur at the same time on different channels using the same power device. There are 8

possible settings, the appropriate setting varies based on the application and connections to

the FFX power devices.

7.2.39

CnOT[2:0]

000

001

010

011

100

101

110

111

PWM slot

1

2

3

4

5

6

7

8

Channel I2S output mapping channels 1 and 2 (0x37)

7.2.40

D7

D6

D5

D4

C2OM2

0

C2OM1

0

C2OM0

1

D3

D2

D1

D0

C1OM2

0

C1OM1

0

C1OM0

0

Channel I2S output mapping channels 3 and 4 (0x38)

7.2.41

D7

D6

D5

D4

C4OM2 C4OM1 C4OM0

0

1

1

D3

D2

D1

D0

C3OM2 C3OM1 C3OM0

0

1

0

Channel I2S output mapping channels 5 and 6 (0x39)

D7

D6

D5

D4

C6OM2

1

C6OM1

0

C6OM0

1

D3

D2

D1

D0

C5OM2

1

C5OM1

0

C5OM0

0

Doc ID 022647 Rev 1

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