DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—
17.6.32Force Event Register for Error Interrupt Status
(FORCE_EVENT_ERR_INT_STAT)—Offset 52h ........................................... 636
17.6.33ADMA Error Status Register (ADMA_ERR_STAT)—Offset 54h ...................... 637
17.6.34ADMA System Address Register (ADMA_SYS_ADDR)—Offset 58h ................ 638
17.6.35initialization Preset Values Register (3.3v or 1.8v)
(PRESET_VALUE_0)—Offset 60h ............................................................. 639
17.6.36Default Speed Preset Values Register (PRESET_VALUE_1)—Offset 62h ......... 639
17.6.37High Speed Preset Values Register (PRESET_VALUE_2)—Offset 64h ............ 640
17.6.38SDR12 Preset Values Register (PRESET_VALUE_3)—Offset 66h ................... 641
17.6.39SDR25 Preset Values Register (PRESET_VALUE_4)—Offset 68h ................... 641
17.6.40SDR50 Preset Values Register (PRESET_VALUE_5)—Offset 6Ah................... 642
17.6.41SDR104 Preset Values Register (PRESET_VALUE_6)—Offset 6Ch ................. 643
17.6.42DDR50 Preset Values Register (PRESET_VALUE_7)—Offset 6Eh................... 643
17.6.43Boot Time-out control register (BOOT_TIMEOUT_CTRL)—Offset 70h ............ 644
17.6.44Debug Selection Register (DEBUG_SEL)—Offset 74h.................................. 644
17.6.45Shared Bus Control Register (SHARED_BUS)—Offset E0h ........................... 645
17.6.46SPI Interrupt Support Register (SPI_INT_SUP)—Offset F0h ........................ 647
17.6.47Slot Interrupt Status Register (SLOT_INT_STAT)—Offset FCh ..................... 647
17.6.48Host Controller Version Register (HOST_CTRL_VER)—Offset FEh ................. 648
18.0 High Speed UART ................................................................................................... 649
18.1 Signal Descriptions .......................................................................................... 649
18.2 Features ......................................................................................................... 650
18.2.1 UART Function...................................................................................... 650
18.2.2 Baud Rate Generator............................................................................. 650
18.3 Use................................................................................................................ 651
18.3.1 DMA Mode Operation............................................................................. 651
18.3.1.1 Receiver DMA ......................................................................... 651
18.3.1.2 Transmitter DMA ..................................................................... 652
18.3.2 FIFO Interrupt-Mode Operation............................................................... 652
18.3.2.1 Receiver Interrupt ................................................................... 652
18.3.2.2 Transmitter Interrupt............................................................... 652
18.3.3 FIFO Polled-Mode Operation ................................................................... 653
18.3.3.1 Receive Data Service ............................................................... 653
18.3.3.2 Transmit Data Service.............................................................. 653
18.3.4 Autoflow Control ................................................................................... 653
18.3.4.1 RTS (UART Output) ................................................................. 653
18.3.4.2 CTS (UART Input) ................................................................... 654
18.4 Register Map................................................................................................... 654
18.5 PCI Configuration Registers............................................................................... 655
18.5.1 Vendor ID (VENDOR_ID)—Offset 0h ........................................................ 655
18.5.2 Device ID (DEVICE_ID)—Offset 2h .......................................................... 656
18.5.3 Command Register (COMMAND_REGISTER)—Offset 4h .............................. 656
18.5.4 Status Register (STATUS)—Offset 6h....................................................... 657
18.5.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .................. 658
18.5.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ....................................... 658
18.5.7 Latency Timer (LATENCY_TIMER)—Offset Dh ............................................ 659
18.5.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 659
18.5.9 BIST (BIST)—Offset Fh .......................................................................... 659
18.5.10Base Address Register (BAR0)—Offset 10h ............................................... 660
18.5.11Base Address Register (BAR1)—Offset 14h ............................................... 660
18.5.12Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h....................... 661
18.5.13Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ....................... 661
18.5.14Subsystem ID (SUB_SYS_ID)—Offset 2Eh................................................ 662
18.5.15Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h .............. 662
18.5.16Capabilities Pointer (CAP_POINTER)—Offset 34h ....................................... 662
Intel® Quark SoC X1000
DS
22
October 2013
Document Number: 329676-001US
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