DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—
21.6
21.7
21.5.2.8 Power Management Configuration RTC Well Register
(PMRW)—Offset 30h ................................................................ 826
21.5.3 ACPI PM1 Block .................................................................................... 827
21.5.3.1 PM1 Status Register (PM1S)—Offset 0h ...................................... 827
21.5.3.2 PM1 Enable Register (PM1E)—Offset 2h...................................... 828
21.5.3.3 PM1 Control Register (PM1C)—Offset 4h ..................................... 829
21.5.3.4 Power Management 1 Timer Register (PM1T)—Offset 8h ............... 830
Legacy GPIO ................................................................................................... 831
21.6.1 Signal Descriptions ............................................................................... 831
21.6.2 Features .............................................................................................. 831
21.6.3 Use..................................................................................................... 831
21.6.4 Register Map........................................................................................ 832
21.6.5 IO Mapped Registers ............................................................................. 832
21.6.5.1 Core Well GPIO Enable (CGEN)—Offset 0h .................................. 833
21.6.5.2 Core Well GPIO Input/Output Select (CGIO)—Offset 4h ................ 833
21.6.5.3 Core Well GPIO Level for Input or Output (CGLVL)—Offset 8h........ 834
21.6.5.4 Core Well GPIO Trigger Positive Edge Enable (CGTPE)—Offset Ch .. 834
21.6.5.5 Core Well GPIO Trigger Negative Edge Enable (CGTNE)—Offset
10h ....................................................................................... 834
21.6.5.6 Core Well GPIO GPE Enable (CGGPE)—Offset 14h ........................ 835
21.6.5.7 Core Well GPIO SMI Enable (CGSMI)—Offset 18h ........................ 835
21.6.5.8 Core Well GPIO Trigger Status (CGTS)—Offset 1Ch ...................... 836
21.6.5.9 Resume Well GPIO Enable (RGEN)—Offset 20h............................ 836
21.6.5.10Resume Well GPIO Input/Output Select (RGIO)—Offset 24h .......... 837
21.6.5.11Resume Well GPIO Level for Input or Output (RGLVL)—Offset 28h . 837
21.6.5.12Resume Well GPIO Trigger Positive Edge Enable (RGTPE)—Offset
2Ch ....................................................................................... 837
21.6.5.13Resume Well GPIO Trigger Negative Edge Enable (RGTNE)—Offset
30h ....................................................................................... 838
21.6.5.14Resume Well GPIO GPE Enable (RGGPE)—Offset 34h ................... 838
21.6.5.15Resume Well GPIO SMI Enable (RGSMI)—Offset 38h .................... 839
21.6.5.16Resume Well GPIO Trigger Status (RGTS)—Offset 3Ch ................. 839
21.6.5.17Core Well GPIO NMI Enable (CGNMIEN)—Offset 40h .................... 840
21.6.5.18Resume Well GPIO NMI Enable (RGNMIEN)—Offset 44h................ 840
Legacy SPI Controller ....................................................................................... 841
21.7.1 Signal Descriptions ............................................................................... 841
21.7.2 Features .............................................................................................. 841
21.7.3 Register Map........................................................................................ 841
21.7.4 Legacy SPI Host Interface Registers ........................................................ 842
21.7.4.1 SPI Status (SPISTS)—Offset 3020h ........................................... 843
21.7.4.2 SPI Control (SPICTL)—Offset 3022h........................................... 844
21.7.4.3 SPI Address (SPIADDR)—Offset 3024h ....................................... 845
21.7.4.4 SPI Data 0 - Lower 32 Bits (SPID0_1)—Offset 3028h ................... 846
21.7.4.5 SPI Data 0 - Upper 32 Bits (SPID0_2)—Offset 302Ch ................... 846
21.7.4.6 SPI Data 1 - Lower 32 Bits (SPID1_1)—Offset 3030h ................... 846
21.7.4.7 SPI Data 1 - Upper 32 Bits (SPID1_2)—Offset 3034h ................... 847
21.7.4.8 SPI Data 2 - Lower 32 Bits (SPID2_1)—Offset 3038h ................... 847
21.7.4.9 SPI Data 2 - Upper 32 Bits (SPID2_2)—Offset 303Ch ................... 847
21.7.4.10SPI Data 3 - Lower 32 Bits (SPID3_1)—Offset 3040h ................... 848
21.7.4.11SPI Data 3 - Upper 32 Bits (SPID3_2)—Offset 3044h ................... 848
21.7.4.12SPI Data 4 - Lower 32 Bits (SPID4_1)—Offset 3048h ................... 848
21.7.4.13SPI Data 4 - Upper 32 Bits (SPID4_2)—Offset 304Ch ................... 849
21.7.4.14SPI Data 5 - Lower 32 Bits (SPID5_1)—Offset 3050h ................... 849
21.7.4.15SPI Data 5 - Upper 32 Bits (SPID5_2)—Offset 3054h ................... 850
21.7.4.16SPI Data 6 - Lower 32 Bits (SPID6_1)—Offset 3058h ................... 850
21.7.4.17SPI Data 6 - Upper 32 Bits (SPID6_2)—Offset 305Ch ................... 850
21.7.4.18SPI Data 7 - Lower 32 Bits (SPID7_1)—Offset 3060h ................... 851
21.7.4.19SPI Data 7 - Upper 32 Bits (SPID7_2)—Offset 3064h ................... 851
21.7.4.20BIOS Base Address (BBAR)—Offset 3070h .................................. 851
Intel® Quark SoC X1000
DS
28
October 2013
Document Number: 329676-001US
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