DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
19.5
19.4.7 Latency Timer (LATENCY_TIMER)—Offset Dh ........................................... 729
19.4.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 730
19.4.9 BIST (BIST)—Offset Fh ......................................................................... 730
19.4.10Base Address Register (BAR0)—Offset 10h .............................................. 731
19.4.11Base Address Register (BAR1)—Offset 14h .............................................. 731
19.4.12Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ...................... 732
19.4.13Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch....................... 732
19.4.14Subsystem ID (SUB_SYS_ID)—Offset 2Eh ............................................... 733
19.4.15Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h.............. 733
19.4.16Capabilities Pointer (CAP_POINTER)—Offset 34h....................................... 733
19.4.17Interrupt Line Register (INTR_LINE)—Offset 3Ch ...................................... 734
19.4.18Interrupt Pin Register (INTR_PIN)—Offset 3Dh ......................................... 734
19.4.19MIN_GNT (MIN_GNT)—Offset 3Eh .......................................................... 735
19.4.20MAX_LAT (MAX_LAT)—Offset 3Fh ........................................................... 735
19.4.21Capability ID (PM_CAP_ID)—Offset 80h................................................... 735
19.4.22Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ........................... 736
19.4.23Power Management Capabilities (PMC)—Offset 82h ................................... 736
19.4.24Power Management Control/Status Register (PMCSR)—Offset 84h .............. 737
19.4.25PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h ..... 738
19.4.26Power Management Data Register (DATA_REGISTER)—Offset 87h .............. 738
19.4.27Capability ID (MSI_CAP_ID)—Offset A0h ................................................. 738
19.4.28Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h .......................... 739
19.4.29Message Control (MESSAGE_CTRL)—Offset A2h ....................................... 739
19.4.30Message Address (MESSAGE_ADDR)—Offset A4h ..................................... 740
19.4.31Message Data (MESSAGE_DATA)—Offset A8h .......................................... 740
19.4.32Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ...................................... 740
19.4.33Pending Bits for MSI (PER_VEC_PEND)—Offset B0h .................................. 741
Memory Mapped Registers................................................................................ 741
19.5.1 I2C* Controller Memory Mapped Registers............................................... 741
19.5.1.1 Control Register (IC_CON)—Offset 0h........................................ 742
19.5.1.2 Master Target Address (IC_TAR)—Offset 4h................................ 743
19.5.1.3 Data Buffer and Command (IC_DATA_CMD)—Offset 10h .............. 744
19.5.1.4 Standard Speed Clock SCL High Count (IC_SS_SCL_HCNT)—Offset
14h....................................................................................... 745
19.5.1.5 Standard Speed Clock SCL Low Count (IC_SS_SCL_LCNT)—Offset
18h....................................................................................... 746
19.5.1.6 Fast Speed Clock SCL High Count (IC_FS_SCL_HCNT)—Offset 1Ch 746
19.5.1.7 Fast Speed Clock SCL Low Count (IC_FS_SCL_LCNT)—Offset 20h . 747
19.5.1.8 Interrupt Status (IC_INTR_STAT)—Offset 2Ch ............................ 747
19.5.1.9 Interrupt Mask (IC_INTR_MASK)—Offset 30h ............................. 749
19.5.1.10Raw Interrupt Status (IC_RAW_INTR_STAT)—Offset 34h ............. 750
19.5.1.11Receive FIFO Threshold Level (IC_RX_TL)—Offset 38h ................. 752
19.5.1.12Transmit FIFO Threshold Level (IC_TX_TL)—Offset 3Ch ............... 752
19.5.1.13Clear Combined and Individual Interrupt (IC_CLR_INTR)—Offset
40h....................................................................................... 753
19.5.1.14Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)—Offset 44h ....... 753
19.5.1.15Clear RX_OVER Interrupt (IC_CLR_RX_OVER)—Offset 48h ........... 754
19.5.1.16Clear TX_OVER Interrupt (IC_CLR_TX_OVER)—Offset 4Ch ........... 754
19.5.1.17Clear RD_REQ Interrupt (IC_CLR_RD_REQ)—Offset 50h............... 755
19.5.1.18Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)—Offset 54h ............ 755
19.5.1.19Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)—Offset 5Ch ........... 756
19.5.1.20Clear STOP_DET Interrupt (IC_CLR_STOP_DET)—Offset 60h ........ 756
19.5.1.21Clear START_DET Interrupt (IC_CLR_START_DET)—Offset 64h ..... 757
19.5.1.22Enable (IC_ENABLE)—Offset 6Ch .............................................. 757
19.5.1.23Status (IC_STATUS)—Offset 70h .............................................. 758
19.5.1.24Transmit FIFO Level (IC_TXFLR)—Offset 74h .............................. 759
19.5.1.25Receive FIFO Level (IC_RXFLR)—Offset 78h ............................... 760
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
25
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