DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel

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DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

21.5.2 ACPI GPE0 Block

Table 115. Summary of I/O Registers—GPE0BLK

Offset

Start

0h

4h

10h

14h

18h

28h

2Ch

30h

Offset End

Register ID—Description

Default

Value

3h

“GPE0 Status Register (GPE0STS)—Offset 0h” on page 821

00000000h

7h

“GPE0 Enable Register (GPE0EN)—Offset 4h” on page 822

00000000h

13h

“SMI Enable Register (SMIEN)—Offset 10h” on page 822

00000000h

17h

“SMI Status Register (SMISTS)—Offset 14h” on page 824

00000000h

1Bh

“General Purpose Event Control Register (GPEC)—Offset 18h” on page 825

00000000h

2Bh

“Power Management Configuration Core Well Register (PMCW)—Offset 28h” on

page 825

00000000h

2Fh

“Power Management Configuration Suspend Well Register (PMSW)—Offset 2Ch” on

page 826

00000000h

33h

“Power Management Configuration RTC Well Register (PMRW)—Offset 30h” on page 826 0000000Bh

21.5.2.1 GPE0 Status Register (GPE0STS)—Offset 0h

Access Method

Type: I/O Register

(Size: 32 bits)

GPE0STS: [GPE0BLK] + 0h

GPE0BLK Type: PCI Configuration Register (Size: 32 bits)

GPE0BLK Reference: [B:0, D:31, F:0] + 4Ch

Default: 00000000h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

Bit

Default &

Range Access

Description

31:18

17

16

15

14

13

12

11

0b

RO

0b

RW/1C

0b

RW/1C

0b

RW/1C

0b

RW/1C

0b

RW/1C

0b

RW/1C

0b

RW/1C

Reserved (RSV2): Reserved.

PCIE Status (PCIE): Set when an Assert SCI message from PCIe Controller is

received.

Remote Management Unit Status (RMU): Set when an Assert SCI message from the

Remote Management Unit is received.

Device Status (SCLT): Set when the SCI signal from Device:20 or Device:21 goes

active.

GPIO Status (GPIO): Set when a GPIO configured for GPE goes active.

External GPE Status (EGPE): Set when the GPE_B signal goes active.

Thermal Status (THRM): Set anytime THRM_B is received at the state defined by

GPEC.TPOL.

Software GPE Status (SWGPE): Set when GPEC.SWGPE is set.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

821

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