DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Default &
Range Access
Description
15
14
13:11
10
9:6
5
4:1
0
0b
RW/1C
0b
RW/1C
0b
RO
0b
RW/1C
0b
RO
0b
RW/1C
0b
RO
0b
RW/1C
Wake Status (WAKE): Resume Well. This bit is set when the system is in an Sx state
and an enable wake event occurs. Upon setting this bit, the Legacy Bridge will transition
the system to the S0 state. This bit is not affected by warm resets
PCIe Wake Status (PCIEWSTS): This bit is set by hardware to indicate that the
system woke due to a PCI Express wakeup event.
Reserved (RSV3): Reserved.
RTC Status (RTC): Resume Well. This bit is set when the RTC asserts IRQ8#, and is
not affected by any other enable bit. This bit is not affected by warm resets
Reserved (RSV2): Reserved.
Global Status (GLOB): Set when SMIS.BRLS is written to '1'. It always cause an SCI
(regardless of PM1C.SCIEN)
Reserved (RSV1): Reserved.
Timer Overflow Status (TO): Set anytime bit 22 of PM1T goes low. See PM1E.TO for
the effect of this bit being set
21.5.3.2
PM1 Enable Register (PM1E)—Offset 2h
Access Method
Type: I/O Register
(Size: 16 bits)
PM1E: [PM1BLK] + 2h
PM1BLK Type: PCI Configuration Register (Size: 32 bits)
PM1BLK Reference: [B:0, D:31, F:0] + 48h
Default: 0000h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Default &
Range Access
Description
15
0b
RO
Reserved (RSV4): Reserved.
14
0b
RW
PCIe Wake Disable (PWAKED): This bit disables the inputs to the PCIEWSTS bit for
waking the system. Modification of this bit has no impact on the value of the PCIEWSTS
bit
13:11
0b
RO
Reserved (RSV3): Reserved.
Intel® Quark SoC X1000
DS
828
October 2013
Document Number: 329676-001US
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