DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Bit
Default &
Range Access
Description
10
0b
RW
RTC Enable (RTC): Resume Well. When set, and PM1S.RTC is set, an SMI#/SCI is
generated. This bit is not cleared by any reset other than RTCRST#, CPU/internal
thermal Trip, or internal watchdog trip
9:6
0b
RO
Reserved (RSV2): Reserved.
5
0b
RW
Global Enable (GLOB): When this bit and PM1S.GLOB are set, SMI#/SCI is generated
4:1
0b
RO
Reserved (RSV1): Reserved.
0
0b
RW
Timer Overflow Enable (TO): When set, and PM1S.TO is set, an SMI#/SCI is
generated
21.5.3.3
PM1 Control Register (PM1C)—Offset 4h
Access Method
Type: I/O Register
(Size: 32 bits)
PM1C: [PM1BLK] + 4h
PM1BLK Type: PCI Configuration Register (Size: 32 bits)
PM1BLK Reference: [B:0, D:31, F:0] + 48h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:14
0b
RO
Reserved (RSV2): Reserved.
13
0b
WO
Sleep Enable (SLPEN): Reads to this bit always return 0. Setting this bit causes the
system to sequence into the Sleep state defined by SLPTYP
Sleep Type (SLPTYPE): Resume Well. This field defines the type of sleep the system
should enter when SLPEN is set. These bits are reset by RTCRST#.
12:10
0b
RW
000b - S0 - On
101b - S3 - Suspend to RAM
110b - S4 - Suspend to Disk
111b - S5 - Soft Off
All other values are reserved
9:3
0b
RO
Reserved (RSV1): Reserved.
2
0b
WO
Global Release (GRLS): Sets SMIS.BIOS when written to 1. This bit always reads as 0
1
0b
RW
Bus Master Reload (BMRLD): This is treated as a scratchpad bit and has no
functionality
0
0b
RW
SCI Enable (SCIEN): When set, events in GPE0_BLK generate SCI. When cleared,
events generate SMI#
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
829
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