DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel

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DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

21.6.5.3

Core Well GPIO Level for Input or Output (CGLVL)—Offset 8h

Access Method

Type: I/O Register

(Size: 32 bits)

CGLVL: [GBA] + 8h

GBA Type: PCI Configuration Register (Size: 32 bits)

GBA Reference: [B:0, D:31, F:0] + 44h

Default: 00000000h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

Bit

Default &

Range Access

Description

31:2

0b

RO

Reserved (RSV): Reserved.

Level (LVL): If the GPIO is programmed to be an output (CGIO.IO[n] cleared), then

1:0

0b

RW

this bit is used by software to drive a value on the pin. 1 = high, 0 = low. If the GPIO is

programmed as an input, then this bit reflects the state of the input signal (1 = high, 0

= low.) and writes will have no effect. The value of this bit has no meaning if the GPIO is

disabled (CGEN.EN[n] = 0).

21.6.5.4

Core Well GPIO Trigger Positive Edge Enable (CGTPE)—Offset Ch

Access Method

Type: I/O Register

(Size: 32 bits)

CGTPE: [GBA] + Ch

GBA Type: PCI Configuration Register (Size: 32 bits)

GBA Reference: [B:0, D:31, F:0] + 44h

Default: 00000000h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

Bit

Default &

Range Access

Description

31:2

0b

RO

Reserved (RSV): Reserved.

Trigger Enable (TE): When set, the corresponding GPIO, if enabled as input via

1:0

0b

RW

CGIO.IO[n], will cause an NMI/SMI/SCI when a 0 to 1 transition occurs. When cleared,

the GPIO is not enabled to trigger an NMI/SMI/SCI on a 0 to 1 transition. This bit has no

meaning if CGIO.IO[n] is cleared (i.e. programmed for output)

21.6.5.5

Core Well GPIO Trigger Negative Edge Enable (CGTNE)—Offset 10h

Access Method

Type: I/O Register

(Size: 32 bits)

CGTNE: [GBA] + 10h

GBA Type: PCI Configuration Register (Size: 32 bits)

GBA Reference: [B:0, D:31, F:0] + 44h

Intel® Quark SoC X1000

DS

834

October 2013

Document Number: 329676-001US

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