DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel

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DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

Bit

Default &

Range Access

Description

31:2

0b

RO

Reserved (RSV): Reserved.

1:0

0b

RW

Enable (EN): When set, the corresponding GPIO, is enabled to generate an SMI and bit

9 of SMI Status register of GPE0 Block will be set.

21.6.5.8

Core Well GPIO Trigger Status (CGTS)—Offset 1Ch

Access Method

Type: I/O Register

(Size: 32 bits)

CGTS: [GBA] + 1Ch

GBA Type: PCI Configuration Register (Size: 32 bits)

GBA Reference: [B:0, D:31, F:0] + 44h

Default: 00000000h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

Bit

Default &

Range Access

Description

31:2

1:0

0b

RO

0b

RW/1C

Reserved (RSV): Reserved.

Trigger Status (TS): When set, the corresponding GPIO, if enabled as input via

CGIO.IO[n], triggered an SMI/SCI/NMI. This will be set if a 0 to 1 transition occurred

and CGTPE.TE[n] was set, or a 1 to 0 transition occurred and CGTNE.TE[n] was set. If

both CGTPE.TE[n] and CGTNE.TE[n] are set, then this bit will be set on both a 0 to 1

and a 1 to=0 transition. This bit will not be set if the GPIO is configured as an output.

21.6.5.9

Resume Well GPIO Enable (RGEN)—Offset 20h

Access Method

Type: I/O Register

(Size: 32 bits)

RGEN: [GBA] + 20h

GBA Type: PCI Configuration Register (Size: 32 bits)

GBA Reference: [B:0, D:31, F:0] + 44h

Default: 0000003Fh

31

28

24

20

16

12

8

4

0

00000000000000000000000000111111

Bit

Default &

Range Access

Description

31:6

0b

RO

Reserved (RSV): Reserved.

5:0

3Fh

RW

Enable (EN): When set, enables the pin as a GPIO.

Intel® Quark SoC X1000

DS

836

October 2013

Document Number: 329676-001US

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